The present invention generally relates to processing a semiconductor substrate. In particular, the present invention relates to measuring both dense and isolated gratings during fabrication in order to determine dense and isolated trench depths to facilitate ascertaining and controlling the microloading effect for an etch process.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the photo mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through the photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Conventional logic devices and flash memory cells allow for a high packing density. Each cell or device may include a core region surrounded by a peripheral region. The core and peripheral regions usually include a series of transistors and source to drain pathways which involve forming dense as well as isolated trench regions. An example of a common transistor found in flash memory cells is a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer.
Furthermore, because shallow trench isolation (STI) has been gradually replacing LOCOS in fabrication of logic devices and memory devices due to its improved utilization of real estate, these products usually include both isolated and dense feature arrays. The combined use of isolated and dense features formed in the core and peripheral regions necessitates the employment of at least two masks in order to achieve the desired trench depths. However, isolated trenches tend to etch faster than those in a dense array. This phenomenon is known as the microloading effect and occurs because more etchant species are consumed locally when etching a larger exposed substrate unit area. In addition, the effect is due to the increasing difficulty to bring etching gases into the narrow-deep structures and to evacuate the etched by-products from the structures.
Typically, these trench depths cannot be measured without breaking the wafer for a cross-sectional inspection by a scanning electron microscope (SEM) or some other end-point detection system. Thus, the wafer is wasted resulting in lost resources and higher production costs as well as decreased fabrication efficiency.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides a system and method for determining the microloading effect in situ a given etch process during fabrication of a semiconductor device wafer. More specifically, the present invention provides a system and method for measuring trench depths associated with isolated and dense feature arrays formed on a product wafer during fabrication of the wafer in order to control microloading and to achieve desired trench depths. This is accomplished in part by monitoring the trench depths of the isolated and dense feature arrays as they are being formed using a scatterometry system. The scatterometry system can be programmed to measure both isolated and dense gratings which correspond to the isolated and dense trench arrays being measured.
By measuring the trench depths, the microloading effect for the particular etch process can be quantified. Thus, the required use of two or more masks for both dense (e.g., core) and isolated (e.g., periphery) areas can be avoided and/or reduced to one mask (or fewer masks) since the microloading effect can be controlled to a desired specification. Therefore, better process control between wafer to wafer and lot to lot is facilitated and obtainable.
One aspect of the present invention relates to a system for determining a microloading effect on a wafer during wafer fabrication. The system includes a semiconductor structure having one or more layers formed over a substrate, the structure being prepared to undergo a fabrication process; a fabrication process assembly for forming one or more features in the semiconductor structure; a microloading characterization system for monitoring the fabrication process assembly, for measuring feature depth, and for processing the measurements in order to determine the microloading effect, the microloading characterization system operable to provide output based on data from a detection apparatus, the detection apparatus being operatively coupled to the microloading characterization system; and a control system for regulating the fabrication process based on the output from the microloading characterization system.
Another aspect of the present invention relates to a system for determining and accommodating for a microloading effect on a wafer layer having isolated and dense features formed therein. The system includes a microloading characterization system which contains a process system for fabricating an isolated array of features in a first region of a semiconductor structure and a dense array of features in a second region of the semiconductor structure, the first region having a first density and the second region having a second density, wherein the first density is less than the second density; a feature depth measurement and monitoring system comprising a detection apparatus for monitoring formation and for measuring feature depth of the arrays; and a processor coupled to the feature depth measurement and monitoring system for collecting and computing the data related to the measured feature depths in order to facilitate determining the microloading effect exhibited by the features. The system further includes a depth control system operatively connected to the processor to receive output relating to the microloading effect from the processor to thereby control one or more feature depth parameter components.
Yet another aspect of the present invention relates to a method for quantifying a microloading effect in situ for a particular process. The method involves providing a semiconductor substrate having at least one layer formed thereon; etching an array of isolated features in a first portion of the layer, the first portion of the layer having a first density; etching an array of dense features in a second portion of the layer, the second portion of the layer having a second density, wherein the first density is less than the second density; and measuring a first depth corresponding to the array of isolated features in the first portion and a second depth corresponding to the array of dense features in the second portion in order to determine the microloading effect.